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Altera_Forum's avatar
Altera_Forum
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18 years ago

vhdl Ram block not compiled and fitted as such

Basically i have written my own simple ram block in vhdl, which is dual port which the cyclone 2 should easily be able to happen. however whenever i compile and fit it the software just puts it into ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Also in the Quartus VHDL/Verilog editor, go to Edit -> Insert Template -> Full Designs, and there should be some RAM examples.