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emaferna
New Contributor
New ContributorVHDL Quartus Simulation, Libraries and Packages
Hello, I have: an entity that implements a circuit for parity check: it have as input an 8 bit std_logic_vector and an std_logic as output. It is located in the folder: C:\User\Desktop\Conversioni...
RichardT_altera
Super Contributor
Super ContributorSorry for idling for some time. May I know do you able to solve the issue by yourself?
Do you need further help on this?
