vhdl programming

During the calculations of the two results, the 4 seven segment displays must show 0000.

1) I have two 7 bit binary outputs(image and word comparison) from scale 100 which are the results of my program. The 3 Seven segment displays from right must show one of the two 7 bit binary numbers in decimal(or unsigned) .Every 3 seconds FPGA will show one of the two numbers. First will show the image percentage and after 3 seconds the word percentage or you can use two switches for the two numbers.In the first seven segment display from the left it will be the number of the choice for example 1 is for image comparison number and 2 for the word comparison number. The other 3 displays will show the decimal number from scale of 100.(0-100).

for example the 4 seven segment displays show this "1050" the 1 in the left is the choice (image) and 050 is the (image) result in decimal or unsigned.

2)Or that i described above with two 6 bit binary numbers I rerange them from scale 32 to scale 100.(..decoding)

I did the second with the two 6 bit numbers it decodes the 6 bit number and the choice.

I am using a counter that counts from 0-63 and so the choice it depends on the 6th bit of the counter.The 6bit goes to a muxs with expansion and so after goes to this decoding.

I would like to hear any suggestions or corrections!

code:

http://pastebin.com/8aazjBd0

any help would be appreciate!