VHDL problem

integer is not an array type, so you cannot use it like and array. Your count signal declaration says you want 11 integers. If you wanted a single integer with 11 bits, you should use the unsigned type (before you do this - delete the non-standard std_logic_unsigned/signed and std_logic_arith libraries from your library list - otherwise you're going to get all sorts of conflicts).

You need:

signal count : unsigned(10 downto 0);

secondly, '9' is a character, not an integer value. change it to

if count = 9 then...

Finally, do not do assignments outside of the clocked part of the process.