Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

VHDL JK FlipFlop Error, Please help

Hello. As you can see in the figure 1, We can make a JK flipflop with 2 ANDs and 2 NORs and two internal signals. So I've written a very simple code in ModelSim to make and simulate a JK FlipF...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

wait on <signal(s)> --wait on signals to change
wait for <time> --wait for the specified ammount of time
wait until <boolean expression>-- wait until the expression is true

In this case I would use wait for to simulate the propagation delay, and set it to 7ns or something like that, with a simulation resolution of 1 ns. But if you have long wait times between the stimuli you could use higher factors for both.