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Altera_Forum
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8 years ago

[VHDL] how to manage lib name depending on the design entry?

Hi All, I want to use the different library names for the same Le's say I have a VHDL file with the following lines: library mylib_1;use mylib_1.abc.all; But, when I'm go...
Altera_Forum's avatar
Altera_Forum
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8 years ago

VHDL has no pre-compiler, like# directives in C or ` directives in verilog. in a `include abc.vh, All these do is literally copy the text from abc.vh into top_level.v and then compile the file.