[VHDL] how to manage lib name depending on the design entry?

import package my_pkg in SV is equivalent to use my_pkg in vhdl.

Compiling a unit into multiple libraries is perfectly fine. Whats the problem here?

vcom -work my_lib1 abc.vhd

vcom -work my_lib2 abc.vhd

Now abc exists in both libraries.

remember, you can refer to items in the same library using work. Work is not a library itself, it can be thought of as a "local library"

So, why not post some code with what you're trying to do. Compiling the same thing into multiple libraries seems like an odd concept to me. A library should be a static thing containing static objects. I dont understand why you would want it in another library.