[VHDL] how to manage lib name depending on the design entry?

"try and explain why you're trying to do what you're doing?" - for different projects, the unit should be compiled into different libraries (library nabes).

"In modelsim you can use the vmap function to map a library to another library" - probably this would be a solution, but as you stated below

"but that wouldnt help if you were refering to mylib_1 inside mylib_2" - is it possible to refer to a package in the library without stating the library name (just a path to the package, like a relative to the directory)

For example,

use ../../mypkg.all