[VHDL] how to manage lib name depending on the design entry?

Why would you want to change the library name? libraries should be collections of related items. Eg. my_math_library would probably contain items that do maths functions. My_axi_lib would contain axi related items. It wouldnt really make sense to have different library names in different projects.

Configurations wouldnt really work, as they still expect a known library name.

In modelsim you can use the vmap function to map a library to another library, but that wouldnt help if you were refering to mylib_1 inside mylib_2.

So try and explain why you're trying to do what you're doing?