vhdl for qpsk modem

I already stated in plain language that:

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Your wording indicates some unclear thoughts. You only need signed thinking.

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You cannot think of signed/unsigned at the same time, it is not just terminology but two different number systems.

Your DAC range is +127 and not +1. You cannot send symbols to a satellite using +1 levels, you need good power signal to get through. Some people talk about +1 in a symbolic(logic) sense.

your input is 8 bits wide. You have to think of communications as one serial bit because you can't(normally) send parallel data buses in sky. so you convert it to serial stream one after the other(starting with MSB or LSB or anywhere you like as long as your receiver knows how to reconstruct your 8 bit values.

So your tasks are:

1) convert 8 bit input to a serial one bit stream

2) convert every two successive bits into a set of IQ values

steps 1 & 2 can be combined like this: at every input sample(valid clk)

think: bit(7) and bit(6) as pair 1, bit(5)& bit(4) as pair 2, bit(3) &bit(2) as pair 3, bit(1) & bit(0) as pair 4.

action:convert each above pair to IQ pair of values as below and send IQ pair 1,IQ pair 2, IQ pair 3, IQ pair 4 sequentially to DAC(now in the form of +127).

your new mapping code can be like this

case sub_data is

.........when "00" =>

...................... I <= std_logic_vector(to_signed(127,8));

......................Q <= std_logic_vector(to_signed(127,8));

.........when "01" =>

...................... I <= std_logic_vector(to_signed(127,8));

......................Q <= std_logic_vector(to_signed(-127,8));

.........when "10" =>

...................... I <= std_logic_vector(to_signed(-127,8));

......................Q <= std_logic_vector(to_signed(127,8));

.........when "11" =>

...................... I <= std_logic_vector(to_signed(-127,8));

......................Q <= std_logic_vector(to_signed(-127,8));

end case;

At the DAC output your analogue signal will hopefully swing full scale voltage

and that is what some call +1 or as you call it bipolar.

The RF engineer will then do the rest. He will map your voltage swings to phase swings. He will generate a really fast frequency e.g. 500MHz sinusoid.(RF engineers live on these sinusoids).

He will change the phase of his sinusoid through 90 degrees for every change of your DAC swing. The final carrier will be sent to power amplifier and into the aerial......In practice he will be very angry if you don't smooth those sharp corners of your +127 symbols in the digital domain. He can shape them in his analogue domain but they don't do that anymore...