vhdl for qpsk modem

Hi,

Your wording indicates some unclear thoughts. You only need signed thinking. You got nothing to do with unsigned. The value 32767 means +32767 and doesn't mean unsigned. In each case of positive or negative values the MSB is used as sign bit(0 for +, 1 for -).

We are talking here about 2's complement as is the case with most fpga signed computations. Check your DAC number system...

Anyway for conversion between std_logic_vector and signed or unsigned

try numeric_std library.

std_logic <=> signed, std_logic <=> unsigned

just use direct cast e.g.

d_signed <= signed(data); -- data is std_logic_vector

d_unsigned <= unsigned(data); -- data is std_logic_vector

d_std_logic <= std_logic_vector(data); -- data is signed

d_std_logic <= std_logic_vector(data); -- data is unsigned

for integer to signed/unsigned you need one stage conversion only,define bitwidth:

I <= to_signed(32767,16); -- I being signed

I <= to_unsigned(32767,16); -- I being unsigned

for integer <=> std_logic_vector you need two stages(cast plus conversion, you need define bitwidth)

I <= std_logic_vector(to_signed(32767,16)); -- 7FFF, 15 bits magnitude

I <= std_logic_vector(to_signed(-32767,16)); -- 8001h, 15 bits magnitude

I <= std_logic_vector(to_unsigned(32767,16)); -- 7FFF, 16 bits magnitude

edit:

some engineers feel that VHDL is too complicated and unfriendly at this type conversion and have raised concerns to ieee. There is certainly room for improvement and mercy.