vhdl for qpsk modem

hi sir..

thank you for your quick reply.

i want to ask you about how to convert std_logic_vector to signed and unsigned...

let say.. when input => '1' then

output <= ---------?? (unsigned)

what are the syntax that can be used to convert to unsigned..

and when input => '0' then

output <= ---------?? (signed)

what are the syntax that can be used to convert to signed..

and what are the library that need to be used.. is it use ieee.std_logic_unsigned and use ieee.std_logic_signed or is it enough to just use ieee.numeric_std.all??

hope to hear from you soon.