vhdl for qpsk modem

Hi,

I am afraid I don't see anything correct or synthesizable in your code.

It is much simpler than that. If your data is a serial bit stream then you need to convert every two bits(every pair) into signed I and Q straightaway:

First convert your stream from 1 bit serial to two bit parallel then use a basic construct to output I/Q(mapping):

assuming you converted your one bit data to the two bit sub_data then:

case sub_data is

.........when "00" =>

...................... I <= std_logic_vector(to_signed(32767,16));

......................Q <= std_logic_vector(to_signed(32767,16));

.........when "01" =>

...................... I <= std_logic_vector(to_signed(32767,16));

......................Q <= std_logic_vector(to_signed(-32767,16));

.........when "10" =>

...................... I <= std_logic_vector(to_signed(-32767,16));

...................... <= std_logic_vector(to_signed(32767,16));

.........when "11" =>

...................... I <= std_logic_vector(to_signed(-32767,16));

......................Q <= std_logic_vector(to_signed(-32767,16));

end case;

notice that I/Q are 16 bits each ready for DAC, use whatever resolution you want for your DAC. The maximum level of 32767 may be too high and you can go lower if you want.

so in short think of serial-parallel converter module followed by mapping module(or do both in one module)

Your serial-to-parallel is a bit more difficult than the mapper. The output pairs must be at half speed of the input data stream and you should pair-up correctly(it is quite easy but many experienced designers could go wrong on pairing boundaries)

You better try it first then if you come up with more code like the one you posted you should get some help before your compiler loses patience.