vhdl for qpsk modem

sir..

i've been able to create vhdl code for each block in qpsk modulator part.

But, there are 1 block that have an error.

it is for unipolar to bipolar.. i need to the incoming data for both I-channel and Q-channel which consist of logic 1 or logic 0. i want to change logic 1 to 1 and logic 0 to -1.

here are the code that i have write for unipolar to bipolar converter.

----------------UNIPOLAR TO BIPOLAR---------------[LOGIC 0=-1, LOGIC 1=1]-------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

USE ieee.std_logic_signed.all;

USE ieee.numeric_std.all;

------------------defines two types: unsigned and signed

ENTITY unipolar_bipolar IS

PORT(

in_i,in_q : IN std_logic_vector (3 downto 0); -------4 bit-------

bI,bQ: OUT std_logic_vector (3 downto 0) -------4 bit-------

);

END unipolar_bipolar ;

ARCHITECTURE beh OF unipolar_bipolar IS

signal p: integer;------------out

signal k: integer;-------------in

signal n: std_logic_vector(3 downto 0);--------------out(final)

signal i:integer; -----------------------for loop 0 until 3 (4 bit)-----------

begin

for i=> '0';

LOOP

i=n;

when in_i(n)=> k & in_q(n)=> k then

case k is

when k ='0' then -----must invert to signed value---[-1]

p <= '1'; -------in std_logic

out_q(n)<= conv_integer(p);

out_i(n) <= conv_integer(p); --------convert into integer(signed)

end case;

case k is

when k ='1' then-----must invert to unsigned value--[1]

p <= '1'; -------in std_logic

out_q(n)<= conv_integer('0'& p);

out_i(n) <= conv_integer('0' & p); --------convert into integer(unsigned)

end case;

n = i+1;

when n='3' loop;

end LOOP;

end beh;

hope you can help me as soon as possible..

thank you so much..