vhdl for qpsk modem

Hi,

Have you tried a search in altera/xilinx site or google(free core).

You can write for a simple qpsk by having some binary stream then map every pair into one symbol(i.e. pick up pairs sequentially and allocate to each a signal value.You will need two channels of this signal(call them I,Q)

Mapping is arbitrary (though predetermined for certain schemes) e.g. you can map as follows(for 8 bits):

00 => I=127,Q=127

01 => I=127,Q=-127

10=> I=-127,-127

11=> I=-127,127

After mapping, you need to shape the pulses, a common filter used is rrcos(root raised cosine in comms, or gaussian in mobile industry).

After shaping you need to pass the signals I,Q to a carrier(upconversion). This is done in a complex multiplier that takes in I/Q and sin/cos of your chosen carrier frequency.

Next you convert the upconverted symbols to analogue(some DACs do the above complex mult as well), if DAC's input speed is more than symbol rate(and this is common)then you need to upsampe the symbols i.e. use interpolation to lift up your signal to DAC speed.

So, there is a lot of learning here. The domodulator is more difficult and has to filter noise,lock to carrier then to clock then reverse the mapping.

kaz