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Altera_Forum's avatar
Altera_Forum
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10 years ago

vhdl for loop and synthesis

Hi, I'm using for i in 0 to idx-1 generate idx could be 0. Is this a problem for Quartus? Thanks.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

No - it is a null range and will be understood. The loop wont get entered.