Altera_Forum
Honored Contributor
13 years agoVHDL error - natural type does not match string literal
Hi,
I am trying to make a simple program which will turn on the green LED when the Key(0) is pressed and when we leave the key, it will be switched off. I am getting this error in the code for some reason though - Error (10515): VHDL type mismatch error at pract.vhd(36): natural type does not match string literal library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity pract is port ( iKEY : in std_logic_vector(0 downto 0); oLEDG: out std_logic_vector(2 downto 0) ); end entity pract; architecture behav of pract is signal sel : std_logic_vector(0 downto 0) := "0"; begin p1 : process(iKEY) begin if(rising_edge(iKEY(0))) then sel <= sel + "1"; end if; end process; p2 : process(iKEY) begin case sel is when "0" => oledg("000") <= '0'; -- this is where i get the error when "1" => oLEDG("000") <= '1'; end case; end process; end behav;