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Honored Contributor
Honored Contributorvhdl don't care problem
Hello. I am making priority encoder in vhdl and I want to use process, case statement and don't care statement. This is my code and compile is done very well. but in model_sim, the output is alw...
Altera_ForumHonored Contributor
Honored Contributoryou didnt say what the error was with the std_match version.
And did you set up the first version to VHDL 2008?
