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Altera_Forum
Honored Contributor
13 years agovhdl don't care problem
Hello. I am making priority encoder in vhdl and I want to use process, case statement and don't care statement. This is my code and compile is done very well. but in model_sim, the output is alw...
Altera_Forum
Honored Contributor
13 years agoHello.. I want to make priority encoder. and I need to use "don't care"
the first code is working well. but when i tested in model_sim. the output is always "000". i thinks if input is "00001--" , and if I make the output "00000100" ,"00000101", "00000110" or "00000111", the output should be "2" = "010". but it's always "000". I use quartus2 version 12.0 and model_sim 12.0 (free_version) (someone said i should use std_match so i made second code using std_match, but it has error. what is the problem?) can anyone give me the priority encoder example using don't care "-"? I am doing this for 1 hours.. but i don't know what's wrong!! ---------------------------------------------------------- ---------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY enco is port( input : in std_logic_vector(7 downto 0); binary_out : out std_logic_vector(2 downto 0)); end enco; ARCHITECTURE arc of enco is begin process(input) begin case input is when "00000001" => binary_out <= "000"; when "0000001-" => binary_out <= "001"; when "000001--" => binary_out <= "010"; when "00001---" => binary_out <= "011"; when "0001----" => binary_out <= "100"; when "001-----" => binary_out <= "101"; when "010-----" => binary_out <= "110"; when "1-------" => binary_out <= "111"; when others => binary_out <= "000"; end case; end process; end arc; ------------------------------------------------------------ ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY enco1 is port( input : in std_logic_vector(7 downto 0); -- 8bit vector 를 이용해 input0~input7를 한번에 만듬 binary_out : out std_logic_vector(2 downto 0)); -- 3bit vector 를 이용해 input1,input2,input3를 한번에 엮음 end enco1; ARCHITECTURE arc of enco1 is begin process(input) begin if std_match(input, "00000001") then binary_out <= "000"; elsif std_match(input, "0000001-") then binary_out <= "001"; elsif std_match(input,"000001--") then binary_out<="010"; elsif std_match(input,"00001---") then binary_out<="011"; elsif std_match(input,"0001----") then binary_out<="100"; elsif std_match(input,"001-----") then binary_out<="101"; elsif std_match(input,"01------") then binary_out<="110"; elsif std_match(input,"1-------") then binary_out<="111"; else binary_out<="000"; end if; end process; end arc;