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Altera_Forum
Honored Contributor
Honored Contributorvhdl don't care problem
Hello. I am making priority encoder in vhdl and I want to use process, case statement and don't care statement. This is my code and compile is done very well. but in model_sim, the output is alw...
Altera_ForumHonored Contributor
Honored Contributorjust checked, modelsim 10.0 should support matching case statements, but you need to compile the code with the -2008 switch. Or modify your modelsim.ini so that
VHDL93 = 2008 (its a silly variable name, but its old)
