Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorvhdl don't care problem
Hello. I am making priority encoder in vhdl and I want to use process, case statement and don't care statement. This is my code and compile is done very well. but in model_sim, the output is alw...
Altera_ForumHonored Contributor
Honored ContributorQ12 is the most up to date. In the menu, you need to set the VHDL version to 2008, or for modelsim, use the -2008 option on vcom when you compile the VHDL (what version of modelsim is it?)
in Quartus: assignments -> settings -> analysis and synthesis settings -> VHDL input -> 2008 The problem is for a while modelsim and quartus supported different things. You need modelsim 10.1 I think for full VHDL 2008 support.
