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Altera_Forum's avatar
Altera_Forum
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13 years ago

vhdl don't care problem

Hello. I am making priority encoder in vhdl and I want to use process, case statement and don't care statement. This is my code and compile is done very well. but in model_sim, the output is alw...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Ok, you cannot use '-' in case statements with older versions of VHDL, but newer versions of Quartus do support the matching case statement from 2008 (ie. using dont cares).

If you have problems with this, you can always use the old fashioned method using the std_match function from the numeric_std library: 


if std_match(input, "00000001") then
elsif std_match(input, "0000001-") then
elsif std_match(input, "000001--") then
--etc