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Altera_Forum
Honored Contributor
Honored Contributorvhdl don't care problem
Hello. I am making priority encoder in vhdl and I want to use process, case statement and don't care statement. This is my code and compile is done very well. but in model_sim, the output is alw...
Altera_ForumHonored Contributor
Honored ContributorI haven't used VHDL in ages but I don't think it supports don't cares in case statements until the 2008 version. So go into the Quartus settings for the project --> Analysis and Synthesis --> VHDL input --> select 2008 version
