Vhdl 'device_family'

Hi Dave,

the script approach to Modelsim is definitely the way to go. I must confess (although not feeling that much guilt) that I haven't used ModelSim yet. I looked into it several times, but always choked on the clumsy-messy-GUI. So I stick with QII 9.1SP2 and use the internal simulator. Now, before you start off, the work I do is rather simple. I build my design from the bottom up using building blocks. These building blocks do simple tasks and are quicker to test with the internal simulator than writing a TB and firing up Modelsim interactively. The building blocks use a standard interconnect, which is actually a subset-like of Avalon-ST. So I am assured that when I connect a string of them together, it will work. I may/will write ST-wrappers so I can later use QSys to connect them, saving some manual work.

But as Altera has dropped the internal simulator, for the newer cyclone families I will have to look in ModelSim again some time in the (near) future when I need to simulate a 'real' project. For the building blocks, I just specify the Cyclone II family and use both the Classic Timing analyser and the internal simulator. But I do use TQ for all projects and the more demanding things like SERDES interfaces, memory PHY and the like. At the time I even simulated a Stratix II GX transceiver using the internal simulator, having the project produce some output which I then copied back as input. It was a bit slow but I was able to test what I needed to.

Best regards,

Josy