Vhdl 'device_family'

Hi Josy,

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first thing I did this morning was to set up the projects and compile/test all three. Made a small change to example three and 'played' it. It works great and I will certainly use this approach in my project.

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Ah, so you do see the error of your ways ... :)

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The only thing to change is that we have different sensors on one side and different interfaces at the other side. In the past we just kept the list of general IO pins, like s[7..0], id[11..0], ld[27..0], and declared most of them all bidirectional and the connected them to their respective pins from the sub-module. This off course provokes a considerable amount of warnings.

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Really, what warnings?

If you have an I/O that you only use an input, just drive it with 'Z', and you won't get warnings about there being no drivers.

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I can add different sections in the share\scripts\constraint.tcl file, set a variable before sourcing the constraint.tcl script and ready we are!

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Another way to work around things like this would be to figure out how to ask Quartus what the pin names in a design are. I think you can do this by splitting the synthesis phases, i.e., (1) elaborate the VHDL, (2) ask for a list of pin names, (3) in the constraints file, generate the pin assignments based on the actual pins used in the design, (4) set unused pins to inputs tri-stated or with pull-ups.

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May I suggest you create a page on the Altera Wiki, what you made up here surpasses the examples in the Altera documentation by far.

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The Altera wiki is by far the ugliest I have ever seen ... there is no 'table of contents', navigation is a nightmare ... but we can do that if you like.

Actually, my approach is not quite so elegant when using SOPC Builder and probably Qsys. I haven't had a chance to sit down and find a solution I am happy with. The basic problem is there is no Tcl command to call these tools, and a simple 'exec' from within Tcl does not work (since I have Cygwin tools installed too). I haven't sat down and looked at it, as its part of a bigger tools building issue I would like to solve; simulation and synthesis testing with multiple versions of Quartus and Modelsim.

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You can avoid that 'unschöne' (unbeautiful?) 'assertion is false' in the Message window by encapsulating a report statement in a process:

  process( all )
      begin
           report "an informational message" ;
      end process ;

It took me a while to find that out.

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Ah, I see what you mean; the VHDL does not look any different really, but the message in the Quartus window looks nicer. I don't usually put assertion messages in the synthesizeable code, but I did in this case to show that the different files were getting sythesized with different LED blink times.

BTW, process(all) is VHDL-2008, so you can add

#  VHDL-2008
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008

to synth.tcl, and you're set!

Thanks for the tip!

Cheers,

Dave