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You could try "AUTO" as the RAM type and then let Quartus select the "right" RAM for you.
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that is where it went wrong : the compiler at one point abused a M-Ram to implement 4096 bits while at the same time using 32 M4Ks to build another fifo and subsequently failing to fit... so I went into the Fifo module and cleared that up, at least for the current project. That code will provoke a warning when we will build our next Cyclone IV design, and I (try to) write code without unnecessary warnings.
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You could add a generic at the top-level called "DEVICE_FAMILY" or "RAM_TYPE" and then pass that down into the design. This is a pain, since you then have to push that generic all the way to the top-level of the design. Another option is to have a configuration package that each design that uses a RAM includes. That VHDL package file would be board specific. Inside this package you can have the constant RAM_TYPE, or multiple names, eg. FIR_COEFFS_RAM_TYPE, RESULTS_RAM_TYPE, etc. Since this package would be included by the components that use RAM, there would be no generics that would have to propagate to the top-level of the design.
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Pushing the RAM-type down as a generic, what were you thinking?
Of course I thought about the possibility of the project package but this is only warranted for true project definitions. It would also mean that for any sub-module project I would have to define a project package, or a default package for each family, that's just clumsy. I can work around by writing a AHDL module that exports the DEVICE_FAMILY for use in VHDL modules, but that AHDL file would have to be manually included too ... I would be tempted to modify the Altera supplied LPM library, as that get's included in about every VHDL file as I tend to use the std_logic_2D a lot. But I can hear the FLAK coming!
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There may be Quartus synthesis directives for RAM use that might be available; I have not used any. But if they existed, and allowed you to specify a RAM by its hierarchical path, then at least that would be independent of the VHDL, and would go in the synthesis script for the design.
Cheers,
Dave
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So it would be nice if Altera provided such a predefined parameter. It is not only is useful for fifos /rams but possibly also in other projects where the family used could matter.
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