But it doesn't work, at least not count regularly.
what do you mean the code or the design ??
A combinational counter description can't be synthesized to any meaningful FPGA logic. That's why you see only gates (LUT) instead of FFs.
Well the compiler just looks at the truth table and for all the possible logic inputs synchronized with rising edge , connects the gates in the LE so that LUT can output that specific reponse. Just like in Karnapgh mapping .
but when i complied the schematic i got the same RTL as the shematic .
Also i wanted to edit my 4-bit counter to count down , guess what in altera components all types of FF have only "Q" output , they are without "/Q" output .