VHDL compiler

I think Bad Omen has covered your question, but Id like to point out several problems with your code:

1. You should no use std_logic_arith and numeric_std in the same bit of code. They conflict. You should use the standard numeric_std rather than the non-standard std_logic_arith.

2. cont is missing from the process sensitivity list. THis is going to create a missmatch between simulation and reality (as the synthesisor ignores the sensitivity list). Also, you cannot write the code the way you have because you are asking it to count infinitly quickly if KEY(1) = '0'. You need a clock in your circuit for a counter.

3. The LEDG assignment should be outside the process.