VHDL compiler

To be clear really the only schematic is that last screenshot you attached. The other two are really just representations of the logic. The LUT is not an optimization, it *is* the implemation of your combinational logic since FPGAs do not have primitives like AND, OR, and NOT gates. instead lookup tables are used where the inputs of your logic wire up to the LUT address line, and the LUT itself is populated with all the possible combinations of outputs. This is not specific to Altera FPGAs, this is how FPGAs work in general. If you look at the device handbook and study the LE or ALUT structure this will probably make more sense.