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Altera_Forum
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15 years ago

VHDL compiler existing

Hi I am using modelsim-altera Starter edition 6.5e along with dsp builder v6.0. when I try to compile vhdl test bench file(created by signal compiler) in modelsim a message appear in the Tra...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

do you really mean existing? or exiting?

If it's exiting, its usually because you have errors. Find out what the errors are and fix them.