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Honored ContributorVHDL Compilation problem : Quartus 11 : Error (12061):
Hi friends, I am new to VHDL , FPGA and Qaurtus. I am getting having a hard time in compiling a VHDL model in Qaurtus ll web edition. The code is below. I compiled it from Modelsim , there it ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The synthesis tool noticed that all of the if statements are in parallel, so it chooses the very last one to implement. It should reduce it to a combinatorial latch that clears all of the output bits once it sees all of the input bits set; there is no way for it to set any of the output bits --- Quote End --- In fact it is inside a process, so each "if" statement will be evaluated by the synthesizer to generate the logic. But I agree that a "case" statement would be more elegant. In both cases it is advisable to also put a default output (either before all the ifs in the original example, or as an "others" case statement) to avoid generation of latches if we forgot an input value.
