Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

VHDL coding issue about AND gate

Hi Dears, It's very simple to draw single bit AND multi-bit bus in schematic design. i.e: http://www.alteraforum.com/forum/attachment.php?attachmentid=10961&stc=1 However, I have to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

--- Quote Start ---

I suggest using if:

if singlebit = '1' then

out <= bus;

else

out < = (others => '0');

end if;

--- Quote End ---

Hi kaz,

Yes, it's a simple way than mine. Thanks!