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Altera_Forum
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11 years ago

VHDL coding issue about AND gate

Hi Dears, It's very simple to draw single bit AND multi-bit bus in schematic design. i.e: http://www.alteraforum.com/forum/attachment.php?attachmentid=10961&stc=1 However, I have to...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Assuming you are using std_logic and std_logic_vector:

Write a function: 

function copyextend( l : std_logic; width : positive) return std_logic_vector is
    variable r : std_logic_vector( width - 1 downto 0);
begin
    for i in 0 to width-1 loop
        r(i) := l;
    end loop;
    return r;
end function ;
PreMHQ1P <= PosMHQAD and copyextend( AddAndDb, 21 ) ;

Put the function in a package and you can re-use it everywhere.