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Altera_Forum
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10 years ago

VHDL coding issue about AND gate

Hi Dears, It's very simple to draw single bit AND multi-bit bus in schematic design. i.e: http://www.alteraforum.com/forum/attachment.php?attachmentid=10961&stc=1 However, I have to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I suggest using if:

if singlebit = '1' then

out <= bus;

else

out < = (others => '0');

end if;