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Honored Contributor
Honored ContributorVhdl code
Hello
I have a code in VHDL that have 2 processes. what will happend when i run the code ? I mean which process will be executed first ? or they are gonna executeed at the same time or what will happen? For example I have this code --library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity counter16step is
port
(
reset,
clk_in : in std_logic;
number_clk : in std_logic_vector (23 downto 0);
p_n : out std_logic
);
end;
architecture arc_counter16step of counter16step is
signal cntr_devider : std_logic_vector (23 downto 0);
signal flag_p_n : std_logic;
begin
process (clk_in, reset)
begin
if reset = '1' then
cntr_devider <= "000000000000000000000000";
elsif rising_edge (clk_in) then
if flag_p_n = '1' then
cntr_devider <= cntr_devider + 1;
end if;
end if;
end process;
process (clk_in, reset)
begin
if reset = '1' then
flag_p_n <= '1';
elsif falling_edge (clk_in) then
if cntr_devider = number_clk then
flag_p_n <= '0';
else
flag_p_n <= '1';
end if;
end if;
end process;
p_n <= flag_p_n;
end;
what will happend here ? which process will run first ?
