Vhdl code

It may be obvious to all, or it may be the jist of the question. When the assignments in the process that uses a clock edge are assigned, they take their next value after the clock edge. So, there is no pass through effect, such as if you use variable assignments. From the simulator's point of view, when the statement is parsed, the assignment's new value to push from the right hand side to the left hand side is scheduled to occur later, even if only time X plus "delta" later.