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Altera_Forum's avatar
Altera_Forum
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8 years ago

VHDL code P2, Is anybody who can help me ?

Hi guys, I have some code for this "project" (photo). I have no idea hot to pair this. Can You help me with port map and signals ? This code is correct ? library IEEE; use IEEE.STD_LOGIC_1164....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

--- Quote Start ---

The template is something like 


<libraries>
entity name_of_module is
<generic and port lists>
end entity;
architecture name_of_architecture of name_of_entity is
<all aliases, signals components and constants>
begin
<processes, signal assignments, port maps etc>
end architecture;

a generic/port map looks like 


label : name_of_component generic map(
    some_gen => 0
)
port map (
    clk => higher_level_clock
);

--- Quote End ---

Finally good reply:) Thank You o much !