Forum Discussion

Honored Contributor

11 years ago

VHDL code help!

Hi guys, I have written out this code, but it gave me error that type R1-R5 is incompatible with A-E. Please help !!!

Honored Contributor

11 years ago

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Please post your modifed code.

The fact the auto-generated testbench still uses std logic makes me beleive you modified nothing.

And you shouldnt need to use the auto-generation - you can write it yourself.

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I modified them manually, and it does not give me errors after i synthesized, so i believe its working?

Can teach me how to write test bench manually without auto generated code?