Forum Discussion

Honored Contributor

11 years ago

VHDL code help!

Hi guys, I have written out this code, but it gave me error that type R1-R5 is incompatible with A-E. Please help !!!

Honored Contributor

11 years ago

--- Quote Start ---

Yes

A : In integer;

--- Quote End ---

Then for the test bench code, the auto generated code still has this

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

signal E : std_logic := '0';

How do i change them?