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Altera_Forum's avatar
Altera_Forum
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12 years ago

VHDL code help!

Hi guys, I have written out this code, but it gave me error that type R1-R5 is incompatible with A-E. Please help !!!
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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All of the A-E inputs are a single std_logic.

R1-R8 are declared as integers.

I dont really know what you're trying to do? why not just input a load of integers?

--- Quote End ---

Is there anyway to declare A-E as integer, or vice versa?