VHDL code for register, to use in a binary multiplication circuit

I wrote a piece a VHDL code for a register (to make a shift register circuit) in a binary multiplication circuit. Once I analyzed it in Quartus II several syntax errors were displayed.

This is my code:

ENTITY memory ISPORT (can_load, can_shift, can_ad, sb_input, ab_input, UserInput : IN BIT;

Out_Bit, Z : OUT BIT);

END memory;

ARCHITECTURE logic OF memory IS SIGNAL State: BIT := '0';

BEGIN

IF (can_load = '1') THEN

State <= UserInput;

ELSE

IF (can_ad = '1')

THEN Z <= State; --Z is the output that goes to the 4 bit adder

State <= ab_input;

END IF;

IF (can_shift = '1') THEN

Out_Bit <= State;

State <= sb_input;

END IF;

END IF;

END logic;

This are the error messages:

Info: *******************************************************************

Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition Info: Processing started: Sun Oct 19 16:28:22 2014 Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition Info: Processing started: Sun Oct 19 16:28:22 2014

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off memory -c memory

Warning (20028): Parallel compilation is not licensed and has been disabled

Error (10500): VHDL syntax error at memory.vhd(9) near text "IF"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at memory.vhd(9) near text "THEN"; expecting "<="

Error (10500): VHDL syntax error at memory.vhd(11) near text "ELSE"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at memory.vhd(12) near text "THEN"; expecting "<="

Error (10500): VHDL syntax error at memory.vhd(15) near text "IF"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"

Error (10500): VHDL syntax error at memory.vhd(16) near text "THEN"; expecting "<="

Error (10500): VHDL syntax error at memory.vhd(19) near text "IF"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"

Info (12021): Found 0 design units, including 0 entities, in source file memory.vhd

I have already checked several books for the correct syntax, and code examples and yet I cannot find where's my mistake.

I also tried to take away the parentheses in sections like this:

IF (can_load = '1') THEN

having something like this:

IF can_load = '1' THEN

but I ended up with most of the same syntax errors.

I'd appreciate any help to solve this issue. Thank you very much.