VHDL 2008 unary or operator

Hi Vicky,

Thanks for responding.

Here is an example that compiles in ModelSim, but not in Quartus.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity MyFlags is
	port
	(
		clock: in std_logic;
		my_flags: in boolean_vector(7 downto 0)
	);
end;
 
architecture V1 of MyFlags is
 
	constant MY_FLAGS_FALSE: boolean_vector(my_flags'range) := (others => false);
	
begin
	process(clock)
	begin
		if rising_edge(clock) then
		
			-- OK: Compiles in Quartus.
			if not(my_flags = MY_FLAGS_FALSE) then
				-- Do something.
			end if;
 
			-- OK: Compiles in Quartus.
			if my_flags /= MY_FLAGS_FALSE then
				-- Do something.
			end if;
 
			-- OK: Compiles in Quartus.
			if my_flags = (my_flags'range => false) then
				-- Do something.
			end if;
 
			-- Not OK: Won't compile in Quartus, but compiles successfully in ModelSim.
			if or my_flags then
				-- Do something.
			end if;
 
			-- Not OK: Won't compile in Quartus, but compiles successfully in ModelSim.
			if or(my_flags) then
				-- Do something.
			end if;
 
		end if;
	end process;
end;

Error messages:

Error (10500): VHDL syntax error at test.vhd(38) near text "or"; expecting "(", or an identifier ("or" is a reserved keyword), or unary operator

Error (10500): VHDL syntax error at test.vhd(43) near text "or"; expecting "(", or an identifier ("or" is a reserved keyword), or unary operator

Error (10500): VHDL syntax error at test.vhd(43) near text "then"; expecting ":=", or "<="

It's not obvious to me what the problem is. Could you enlighten me?

Thanks,

Tim.