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StefanB's avatar
StefanB
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5 years ago

vhdl 2008: read output / unary operator

Hi Attached you will find a VHDL-file, which implements an FSM and uses the function "next_crc16_d8(..)" to calculate the CRC. The file compiles fine for Questa, but fails in QuartusPrime 18.1 on...
KennyT_altera's avatar
KennyT_altera
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5 years ago

@JC_FPGA let me know if you interested as well, if yes, you will have to provide us your email address for further communication.


JC_FPGA's avatar
JC_FPGA
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5 years ago

DM sent