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Altera_Forum
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11 years ago

VHDL : Problem with 4-Bit Adder and Subtractor !

Hi I want to make a 4-Bit Adder and Subtractor with VHDL I have created 1-Bit Full-Adder , XOR Gate ( for Subtract ) and a 4-Bit Adder as shown below : Full-Adder : LIBRARY ieee; USE i...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Yes, I`m sure , when Sum is INOUT this problem occurs !

I tested ALU Directly , problem is in ALU

may you test ALU and find the problem ?

...

I have a 4 bit Adder , A and B are 4-Bit Registers , As and Bs are sign bit of A and B ( A + As = 5 Bit ) , I want to Add or Sub A and B, and calc the sign bit of the result with comparing As and Bs , at the end , the result should store in A and As

this is a simple scenario but i can`t find the problem !