VHDL : Problem with 4-Bit Adder and Subtractor !

The simple Chart is like this :

http://www.alteraforum.com/forum/attachment.php?attachmentid=10757&stc=1

I made some changes

New ALU Code :

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY ALU IS
  PORT(
    --Clk  : IN STD_LOGIC;
    A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    As : INOUT STD_LOGIC;
    Bs : IN STD_LOGIC;
    Mode : IN STD_LOGIC;
    AVF : OUT STD_LOGIC
  );  
END ALU;
ARCHITECTURE Declare OF ALU IS
COMPONENT Adder_4_Bit IS
  PORT(
    A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    Mode : IN STD_LOGIC;
    Sum  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    COut : OUT STD_LOGIC
  );  
END COMPONENT;
SIGNAL E : STD_LOGIC;
SIGNAL Sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN   
  
 Add : Adder_4_Bit PORT MAP(A, B, Mode, Sum, E);   
 PROCESS(As, Bs, A, B, Mode)
 BEGIN   
  CASE Mode IS
   WHEN '0' =>
     IF ((As XOR Bs) = '1') THEN                                
       AVF <= '0';
       IF (E = '1') THEN
         IF (Sum = "0000") THEN
           As <= '0';
         END IF;
       ELSE           
         Sum <= (NOT Sum) + "0001";
         As <= NOT As;
       END IF;
     ELSE
       AVF <= E;
     END IF;
        
   WHEN '1' =>
     IF ((As XOR Bs) = '1') THEN                                  
       AVF <= E;        
     ELSE       
       AVF <= '0';
       IF (E = '1') THEN
         IF (Sum = "0000") THEN
           As <= '0';
         END IF;
       ELSE
         Sum <= (NOT Sum) + "0001";
         As <= NOT As;
       END IF;      
     END IF;
     
   WHEN Others =>  
    --   
  END CASE;
            
 END PROCESS; 
  
END Declare;

New Test Bench Code :

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY ALU_Test_Bench IS
 
END ALU_Test_Bench;
ARCHITECTURE Declare OF ALU_Test_Bench IS
COMPONENT ALU IS
  PORT(
    --Clk  : IN STD_LOGIC;
    A : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    As : INOUT STD_LOGIC;
    Bs : IN STD_LOGIC;
    Mode : IN STD_LOGIC;
    AVF : OUT STD_LOGIC
  );   
END COMPONENT;
SIGNAL Xs, Ys, M, Av : STD_LOGIC;
SIGNAL X, Y : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
  
  ALU_PM : ALU PORT MAP(X, Y, Xs, Ys, M, Av);
 
  Mode_Process : PROCESS
  BEGIN
  M <= '1';
  WAIT FOR 10 ns;
  
  M <= '0';
  WAIT FOR 10 ns;
    
  END PROCESS;
  
  Calc_Process : PROCESS
  BEGIN       
     
   X <= "0010";
   Y <= "1011";
   Xs <= '0';
   Ys <= '1';
   WAIT FOR 20 ns;
   
   X <= "0110";
   Y <= "0011";
   Xs <= '1';
   Ys <= '1'; 
   WAIT FOR 20 ns; 
    
   X <= "0010";
   Y <= "1011";
   Xs <= '0';
   Ys <= '1';
   WAIT FOR 20 ns; 
      
  END PROCESS;
  
END Declare;

but when I tried to simulate test bench, got the result below !! :

http://www.alteraforum.com/forum/attachment.php?attachmentid=10758&stc=1

Why the X value is 'U' ?!?

what goes wrong with my Test-Bench ?

* Edit :

I tested ALU , Problem is in ALU that Set Value of Sum to 'U'

I can`t find the problem ! , help please ! ...