Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

VHDL : Problem with 4-Bit Adder and Subtractor !

Hi I want to make a 4-Bit Adder and Subtractor with VHDL I have created 1-Bit Full-Adder , XOR Gate ( for Subtract ) and a 4-Bit Adder as shown below : Full-Adder : LIBRARY ieee; USE i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Well you have a test bench, so you can easy follow your signals backwards and debug it yourself.

But I will note that your first code is not synthesisable. You cannot have wait statements like you have inside a process. What do you expect the circuit to look like? Have you drawn the circuit diagram before you wrote the code?