VHDL : Problem with 4-Bit Adder and Subtractor !

I made some changes

I made a ALU unit as :

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY ALU IS
  PORT(
    --Clk  : IN STD_LOGIC;
    A, B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
    Sel  : IN STD_LOGIC;
    AOut : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
    AsO  : OUT STD_LOGIC
  );  
END ALU;
ARCHITECTURE Declare OF ALU IS
COMPONENT Adder_4_Bit IS
  PORT(
    A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    Mode : IN STD_LOGIC;
    Sum  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    COut : OUT STD_LOGIC
  );  
END COMPONENT;
SIGNAL As, Bs, E, AVF : STD_LOGIC;
SIGNAL XA, XB, Sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Mode : STD_LOGIC;
BEGIN   
  
 Add : Adder_4_Bit
 PORT MAP(XA, XB, Mode, Sum, E);   
 PROCESS
 BEGIN
 
 As <= A(4);
 Bs <= B(4);
 
 XA <= A(3 DOWNTO 0);
 XB <= B(3 DOWNTO 0);  
  
  CASE Sel IS
   WHEN '0' =>
     IF ((As XOR Bs) = '1') THEN                   
       Mode <= '1';              
       AVF <= '0';
       WAIT ON Sum;
       IF (E = '1') THEN
         IF (Sum = "0000") THEN
           As <= '0';
         END IF;
       ELSE           
         Sum <= (NOT Sum) + "0001";
         As <= NOT As;
       END IF; 
     ELSE
       Mode <= '0';
       WAIT ON Sum;
     END IF;
     
     AOut <= Sum;
     AsO  <= As;  
        
   WHEN '1' =>
     IF ((As XOR Bs) = '1') THEN              
       Mode <= '0';
       WAIT ON Sum;                     
       AVF <= E;        
     ELSE       
       Mode <= '1';
       WAIT ON Sum;
       AVF <= '0';
       IF (E = '1') THEN
         IF (Sum = "0000") THEN
           As <= '0';
         END IF;
       ELSE
         Sum <= (NOT Sum) + "0001";
         As <= NOT As;
       END IF;      
     END IF;
     AOut <= Sum;
     AsO  <= As;
   WHEN Others =>  
    --   
  END CASE;
            
 END PROCESS; 
  
END Declare;

and A Test Bench like this :

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY ALU_Test_Bench IS
 
END ALU_Test_Bench;
ARCHITECTURE Declare OF ALU_Test_Bench IS
COMPONENT ALU IS
  PORT(
    --Clk  : IN STD_LOGIC;
    A, B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
    Sel  : IN STD_LOGIC;
    AOut : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
    AsO  : OUT STD_LOGIC
  );  
END COMPONENT;
SIGNAL Xs, S : STD_LOGIC;
SIGNAL X, Y, O : STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
  
  ALU_PM : ALU PORT MAP(X, Y, S, O, Xs);
 
  Main_Process : PROCESS
  BEGIN       
   WAIT FOR 100 ns;  
   X <= "00010";
   Y <= "11011";
             
   S <= '0';
   WAIT FOR 30 ns;
   S <= '1';
   WAIT FOR 30 ns;
   WAIT FOR 100 ns;  
   X <= "01110";
   Y <= "10011";
             
   S <= '0';
   WAIT FOR 30 ns;
   S <= '1';
   WAIT FOR 30 ns; 
   
   WAIT FOR 100 ns;  
   X <= "10011";
   Y <= "11111";
             
   S <= '0';
   WAIT FOR 30 ns;
   S <= '1';
   WAIT FOR 30 ns; 
      
  END PROCESS;
  
END Declare;

As i say , i want to model the algorithm i posted in first post

there is some problem ...

for example when i simulate and run test bench , there is no output value in O and Xs !

I know the problem is in ALU and Test Bench

I changed ALU many times and tested many ways but all times some things goes wrong !

If you want to code that algorithm , which units you will create or at all what will you create ?! and how will you code that ?!

thanks for your help ...