Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

VHDL - (4-bit Adder) Combinational Logic: Hierarchical Design

Hi, I'm new to VHDL and have an issue with a required project and I was hoping someone could help with my code. I'm unable to get my program to compile and not exactly sure what I'm doing wrong. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Tricky,

Appreciate the info, it was really informative. Also, I really like the style of the code you provided, definitely looks much cleaner, but I'm not sure if the code would work exactly with my project. I probably should've mentioned that the project is an assignment and most of the code that I posted was provided so I'm sorta stuck with it. The code I provided was the bottom part between the BEGIN & END imp.

I tried using the code you provided just to see how it would work and I received the following error code. Sure it was something I probably did being a newbie.

Error (10481): VHDL Use Clause error at Adder4.vhd(25): design library "work" does not contain primary unit "Adder1"

Thanks