VHDL - (4-bit Adder) Combinational Logic: Hierarchical Design

You have connected a signal called cIn to the A1 instance of Adder1, but you have no local signal called cIn.

PS> There are 2 coding styles I would not recommend here:

1. Positional association. You can easily put signals in the wrong place. Much better to use named association:

2. I also dont like the use of components when the source is also VHDL. It means you have to maintain the same code in 2 places (and they must match). And you wont find problems until the elaboration phase (which for big designs can take a few minutes). Using direct instantiation means you can find the problem in seconds rather than minutes as the compiler checks the code directly against the entity.

A3: entity work.Adder1 --direct instantiation, no need for component.
port map (
a => a(2), 
b => b(2), 
cIn => carry_sig(1), 
sum => sum(2), 
cOut => carry_sig(2)
);