VGA sync circuit

this lines:

begin

--register

process(clk,reset)

begin

if (reset='1') then

mod2_reg <='0';

v_count_reg <=(others=>'0');

h_count_reg <=(others=>'0');

v_sync_reg <='0';

h_sync_reg <='0';

elsif(clk'event and clk='1')then

mod2_reg <=mod2_next;

v_count_reg <=v_count_next;

h_count_reg <=h_count_next;

v_sync_reg <=v_sync_next;

h_sync_reg <=h_sync_next;

end if;

end process;

inferres register ( flip-flops ). The vector h_sync_next is the "d" input of a register. And the output is h_count_reg. So when a rising edge arrives, the value of h_sync_next ( incremented value ) gets latched on h_count_reg. The fundamentals of any synchronous circuit.